CLKDIV=CMP_PCLK, S_MODE=BYPASS_INPUT_FILTER
Comparator 0 pin filter set-up
| S_MODE | Digital filter sample mode. 0 (BYPASS_INPUT_FILTER): Bypass input filter. 1 (1_CLOCK_CYCLE): 1 clock cycle. Input pulses shorter than one filter clock are rejected. 2 (2_CLOCK_CYCLES): 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 3 (3_CLOCK_CYCLES): 3 clock cycles. Input pulses shorter than three filter clocks are rejected. |
| CLKDIV | Select clock divider for comparator clock CMP_PCLK. 0 (CMP_PCLK): CMP_PCLK. 1 (CMP_PCLKDIV2): CMP_PCLK/2. 2 (CMP_PCLKDIV4): CMP_PCLK/4. 3 (CMP_PCLKDIV8): CMP_PCLK/8. 4 (CMP_PCLKDIV16): CMP_PCLK/16. 5 (CMP_PCLKDIV32): CMP_PCLK/32. 6 (CMP_PCLKDIV64): CMP_PCLK/64. |
| RESERVED | Reserved |